DESIGN OF A TUNABLE REPLICA OSCILLATOR (TRO) FOR DYNAMIC FREQUENCY ADJUSTMENT IN A 28 NM CMOS PROCESS

ESTEVEZ ESPINOSA,  JOHAN CAMILO; BALLESTEROS SANTOS, ANDRES FELIPE

Publicación:
DESIGN OF A TUNABLE REPLICA OSCILLATOR (TRO) FOR DYNAMIC FREQUENCY ADJUSTMENT IN A 28 NM CMOS PROCESS

dc.contributor.advisor	CABALLERO BARAJAS, EDUARDO
dc.contributor.advisor	ARDILA OCHOA, JAVIER FERNEY
dc.contributor.author	ESTEVEZ ESPINOSA, JOHAN CAMILO
dc.contributor.author	BALLESTEROS SANTOS, ANDRES FELIPE
dc.contributor.evaluator	AMAYA PALACIO, JOSE ALEJANDRO
dc.contributor.evaluator	MANTILLA RIOS, ALEX JULIAN
dc.date.accessioned	2026-06-12T13:27:40Z
dc.date.created	2026-06-09
dc.date.issued	2026-06-09
dc.description.abstract	The OnChip research group is developing a Unified Voltage and Frequency Regulator (UVFR) system to improve energy management efficiency in integrated digital circuits. A key component of this system is the Tunable Replica Oscillator (TRO), which dynamically adjusts the clock frequency to match the delay of the critical path in a digital circuit. However,the design of the TRO presents challenges related to power supply sensitivity and accurate replication of the critical path. This work focuses on the design of a TRO circuit that involves analyzing, exploring, designing, and validating the system through rigorous simulations using a 28 nm TSMC standard CMOS process.
dc.description.abstractenglish	The OnChip research group is developing a Unified Voltage and Frequency Regulator (UVFR) system to improve energy management efficiency in integrated digital circuits. A key component of this system is the Tunable Replica Oscillator (TRO), which dynamically adjusts the clock frequency to match the delay of the critical path in a digital circuit. However,the design of the TRO presents challenges related to power supply sensitivity and accurate replication of the critical path. This work focuses on the design of a TRO circuit that involves analyzing, exploring, designing, and validating the system through rigorous simulations using a 28 nm TSMC standard CMOS process.
dc.description.degreelevel	Pregrado
dc.description.degreename	Ingeniero Electrónico
dc.format.mimetype	application/pdf
dc.identifier.instname	Universidad Industrial de Santander
dc.identifier.reponame	Universidad Industrial de Santander
dc.identifier.repourl	https://noesis.uis.edu.co
dc.identifier.uri	https://noesis.uis.edu.co/handle/20.500.14071/47931
dc.language.iso	eng
dc.publisher	Universidad Industrial de Santander
dc.publisher.faculty	Facultad de Ingeníerias Fisicomecánicas
dc.publisher.program	Ingeniería Electrónica
dc.publisher.school	Escuela de Ingenierías Eléctrica, Electrónica y Telecomunicaciones
dc.rights	info:eu-repo/semantics/openAccess
dc.rights.accessrights	info:eu-repo/semantics/openAccess
dc.rights.coar	http://purl.org/coar/access_right/c_abf2
dc.rights.creativecommons	Atribución-NoComercial-SinDerivadas 4.0 Internacional (CC BY-NC-ND 4.0)
dc.rights.license	Atribución-SinDerivadas 2.5 Colombia (CC BY-ND 2.5 CO)
dc.rights.uri	https://creativecommons.org/licenses/by-nc/4.0/
dc.subject	UVFR
dc.subject	TRO
dc.subject	Reloj Adaptativo
dc.subject	Seguimiento del Camino Crítico
dc.subject	Gestión de Potencia
dc.subject	Oscilador en Anillo
dc.subject.keyword	UVFR
dc.subject.keyword	TRO
dc.subject.keyword	Adaptive Clocking
dc.subject.keyword	Critical Path Matching
dc.subject.keyword	Power Management
dc.subject.keyword	Ring Oscillator
dc.title	DESIGN OF A TUNABLE REPLICA OSCILLATOR (TRO) FOR DYNAMIC FREQUENCY ADJUSTMENT IN A 28 NM CMOS PROCESS
dc.title.english	DESIGN OF A TUNABLE REPLICA OSCILLATOR (TRO) FOR DYNAMIC FREQUENCY ADJUSTMENT IN A 28 NM CMOS PROCESS
dc.type.coar	http://purl.org/coar/resource_type/c_7a1f
dc.type.hasversion	http://purl.org/coar/version/c_b1a7d7d4d402bcce
dc.type.local	Tesis/Trabajo de grado - Monografía - Pregrado
dspace.entity.type	Publication