The OnChip research group is developing a Unified Voltage and Frequency Regulator (UVFR) system to improve energy management efficiency in integrated digital circuits. A key component of this system is the Tunable Replica Oscillator (TRO), which dynamically adjusts the clock frequency to match the delay of the critical path in a digital circuit. However,the design of the TRO presents challenges related to power supply sensitivity and accurate replication of the critical path. This work focuses on the design of a TRO circuit that involves analyzing, exploring, designing, and validating the system through rigorous simulations using a 28 nm TSMC standard CMOS process.